Making Modern Memory Controllers Programmable Improves Their Versatility and Efficiency. However, the Stringent Latency and Throughput Requirements of Modern

......The off-chip memory subsystem is a significant performance, power, and quality-of-service (QoS) bottleneck in modern computers, necessitating a high-performance memory controller that can overcome DRAM (dynamic randomaccess memory) timing and resource constraints by orchestrating data movement between the processor and main memory. Contemporary DDRx (double data rate memory interface technology) memory controllers implement sophisticated address mapping, command scheduling, power management, and refresh algorithms to maximize system throughput and minimize DRAM energy, while ensuring that system-level QoS targets and real-time deadlines are met. The conflicting requirements imposed by this multiobjective optimization, compounded by diversity in both workload and memory system characteristics, make high-performance memory controller design a significant challenge. A promising way of improving the versatility and efficiency of a memory controller is to make it programmable—a proven technique that has seen wide use in other control tasks ranging from direct memory access (DMA) scheduling to NAND flash and directory control. In these and other architectural control problems, programmability allows the processor designers to customize the controller on the basis of system requirements and performance objectives, perform in-field firmware updates to the controller, and set up applicationspecific control policies. Unfortunately, the stringent latency and throughput requirements of modern DDRx devices have rendered such programmability largely impractical, confining DDRx controllers to fixed-function hardware. As a result, contemporary memory controllers are invariably confined to implementing DRAM control policies in hardwired, fixed-function hardware blocks. Pardis (programmable architecture for the DDRx interfacing standards) is the first programmable memory controller that provides sufficiently high performance to make the firmware implementation of DDRx control policies practical. Pardis divides the tasks associated with high-performance DRAM control among a request processor, a transaction processor, and dedicated command logic. The request and transaction processors mmi2013030106.3d 15/5/013 16:20 Page 106